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publié le 21 avril 2018 Beauté › Troc entre nous

Computex 2013 Acer got Computex 2013 off to a less-than-spectacular start this morning with the launch of the world’s first “one-handed” Windows 8 tablet, a 5.7in phablet and a new version of its flagship ultrabook.In a relatively subdued press conference, Acer president Jim Wong unveiled the company’s latest attempt to get back into the personal computing caper now that tablets and smartphone hybrids have seen punters ignore upgrades to Acer's PC line.First up was the 8.1in Iconia W3, a Windows 8 tablet running Microsoft Office Home & Student 2013 and touted for offering a “desktop in one hand”.At 540 grams and just 11.35mm thick, it’s going to appeal to mobile workers for whom portability is key, although an optional full-sized keyboard will make it a little less portable.The Intel Atom Z2760-powered device features front-and-rear-facing 2MP cameras, a 1280x800 resolution screen, eight hours of battery life and will come with 32 or 64GB internal storage, starting at around €329.

The suspicion and borderline hostility shown by the firm to partner Microsoft over the past year, after the launch of Redmond’s Surface laptop, was not in evidence at this morning's event and it was all smiles as a Microsoft representative took the stage to big up the Windows 8-related productivity benefits of the W3.With single and dual SIM options, a quad-core 1.5 GHz Mediatek processor, and a day's worth of battery power, the handset could also appeal to business, even if it does run Android Jelly Bean.A particularly nifty productivity-enhancing feature demoed on stage is the “float” UI, which allows the user to multi-task, switching between camera, phone, notes and other apps with ease thanks to a small floating shortcut icon.Also touted is an 88° wide viewing angle for improved video conferencing, a voice activated phone unlocking function, and an Auto Profile feature which will automatically set the handset’s profile depending on its location.The 1GB device will be available in Q3, although pricing isn’t yet available.Not content with that little lot, Acer also unveiled a new version of its flagship 13.3in S7 ultrabook with an enhanced keyboard, improved battery life and quieter performance, as well as a “little brother”, the S3 ultrabook.

“In the new PC world users are becoming smarter and demanding a significantly enhanced overall user experience,” said Acer CEO JT Wang. “If you don’t do that they don’t buy.” Back in 2011, Intel pledged Haswell would cut the power consumed by a laptop when its lid was closed to five per cent, a promise it reiterated at IDF 2012 last September. Haswell employs a number of tricks in its bid to make good on the company’s promise and deliver what it claims is “Intel’s biggest increase in battery life generation on generation”. That means, it says, doubling or even tripling the battery life achievable with an Ivy Bridge chip, and a 20x stand-by power reduction when compared to a Sandy Bridge machine.The shift to a smaller production process, from Sandy Bridge’s 32nm to 22nm, introduced last year with the Sandy Bridge re-spin, Ivy Bridge, helps a lot here. Intel has refined its 22nm process further, cutting the current leaking from its tri-gate transistors to between a half and a third of what it was in Ivy Bridge, and dropping the voltage required to drive each transistor. Bringing more IO control onto the processor die - all the digital display interfacing is now handled by the CPU - helps cut the system’s overall power draw a bit, but Haswell goes further.

First, it has an on-board voltage regulator, which Intel calls its “Fully Integrated Voltage Regulator (FIVR)”. This allows Haswell’s key sections - the CPU cores, the GPU, the IO and memory controllers, and the units that manage them all - to be fed from a single voltage input. Previously there were five separate inputs all fed from voltage regulators on the motherboard. Beyond reducing motherboard component counts and thus cost and power draw, the advantages of an integrated voltage regulator are faster power switching because there’s less oscillation around the target voltage when the switch takes place.Separate voltage planes mean that deeper sleep states can be reached too, by completely shutting down parts of the core that aren’t required. “Everything that is not needed is turned off!” boast the engineers. The chip transitioned in and out of these states more quickly: Haswell is 25 per cent faster than Ivy Bridge in this regard, Intel has said in the past.

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Placed on the chip, the FIVR can be closely tied into the processor’s power management system, which in Haswell uses the chip’s understanding of what it’s being asked to do in order to exploit more power-reduction opportunities. It can see, says Intel, that for a certain period of time parts of the chip - and even some system components - can be put into low-power states or turned off altogether to save energy. After the calculated duration, Haswell’s power manager - Intel calls it a Power Optimizer - wakes them up again. Smarter power management isn’t merely central to making Haswell-based systems’ batteries last longer, but it also makes them more useful and responsive the way an ARM-powered mobile devices can be: constantly picking up messages, even when sleeping, and ready for use in a near instant. That’s a crucial facility laptops must gain if they aren’t to be overshadowed by tablets any more than they already are.

Haswell delivers three of power states that form a sub-set of the standard S0, ‘awake’ state that has been part of the ACPI (Advanced Configuration and Power Interface) specification for years. Instead of remaining fully awake in the S0 state, Haswell drops to the equivalent of existing S1 to S3 sleep mode power consumption levels but keeps an eye open, as it were, so it’s ready to handle user interaction. Think of it as a quick nap while the user pauses to read something on screen, or a deeper doze when the machine’s not being used. In each case the Power Optimizer can quickly bring everything back so the user doesn’t notice it hasn’t been entirely paying attention. So when laptop’s lid is closed, the system will drop to a power consumption level existing machines reach only when hibernating - the S3 state - but the system is nonetheless sufficiently awake to be ready to use by the time the user has lifted the lid, and to periodically poll for messages and other net-delivered data. Haswell delivers “idle power approaching [that of] tablet CPUs”, claims Intel.

Latency data from compatible system components allows the Haswell Power Optimizer to know how long it takes each of them to wake up, ensuring the whole system - or at least those parts of it required to give the user immediate operation - are all ready at the same time. To gain the full benefit, then, notebook makers will have to equip their kit with components that can give Haswell that latency information, so expect Intel to exert even more control than it already does, by certifying which components give full Haswell Power Optimizer compatibility. Latency informations also helps Power Optimizer schedule tasks to align them, resulting in burst of activity bookended by periods of longer power-saving inactivity. Windows 8 already supports this kind of operation on order to keep its new UI live tiles updated, a technique Microsoft calls Connected Standby, but Haswell extends it to Windows desktop apps too and integrates it into its more modern sleep state set-up.

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Unlike Ivy Bridge, Haswell maintains separate clock signals for the cores, for the GPU, and for the L3 cache and the ring bus that links it to those other two modules. At the cost of cache performance, this means you can keep the cores slow when only the GPU needs to exchange data with the cache, saving power. Slowing down the core, because its frequency isn’t pegged to the GPU, means, conversely, there’s power left over to raise the GPU’s frequency, if it’s required.Each core itself is largely the same as those found in Ivy Bridge processors. Intel has improved the front end - the bit that pulls in the x86 instructions that programs are compiled into before converting them into micro ops, which are the chip’s native instruction set - so it’s better able to anticipate in which direction upcoming branches in the code will take the execution stream, but Intel does this with every new generation of its architecture.

After conversion from x86, the micro ops are juggled into a new order that allows the core’s many instruction-processing engines to kept well fuelled without (hopefully) breaking data dependencies in the original program, which can happen if an out-of-order action changes the value of variable beyond what another instruction was expecting it to be. Haswell has more capacity than its predecessors to sort through the micro ops to see how many can be executed in parallel. It has more core register space for temporary data. Where Ivy Bridge had two, 28-op buffers, one per thread, from which micro ops were routed to free maths units, Haswell cores have one, 56-op buffer with eight output ports rather than six, the better to keep as many micro ops flowing as possible.The array of available maths units has again been tweaked to accommodate the loading Intel’s modelling of real-world workloads is most likely to require. That’s a moveable feast, of course. New applications and uses may have come into play which the chip engineers didn’t take into account, or program patterns they did anticipate and designed for may have fallen out of fashion.

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